Railtrack OD on DMP Di1
Embedded dual-model railway obstruction pipeline running BiSeNetV2 and YOLOv8s on the DMP Di1/iCatch A3000 NPU with live camera streaming and integration into a fleet DMS/ODS dashboard.
Outcomes
- ●Stable 4.5–5.0 FPS dual-model concurrency on DMP Di1 NPU
- ●End-to-end Glass-to-Dashboard latency under 200ms
- ●YOLO detection confidence recovered from <0.10 (distorted) to >0.87 (letterboxed)
- ●60+ minute continuous run validated with zero memory leaks or frame drops
Portfolio Highlights
- →Ported a dual-model railway safety pipeline (BiSeNetV2 + YOLOv8s) to the DMP Di1 NPU, achieving production-grade stability and <200ms latency.
- →Designed a hybrid hardware/software preprocessing architecture that recovered 80% detection confidence lost to hardware-specific distortion.
- →Developed a complete embedded DevOps workflow, including Docker-based cross-compilation and automated rsync deployment.
Snapshot
- Period: April 2026
- Domain: Embedded AI, Edge Computer Vision
- Target Hardware: DMP Di1 SoC / iCatch A3000 NPU
- AI Orchestration: Developed with Gemini CLI for system-level orchestration and build automation; manual C++ implementation of NPU-specific memory management and preprocessing.
- Status: Production-ready handoff
The Business Problem
Railway safety requires real-time obstruction detection with zero room for latency or false negatives. Moving from research-grade Python scripts to an embedded edge device is a major technical hurdle—standard "plug-and-play" AI models often fail due to hardware-specific distortion and limited NPU instruction sets.
Technical Deep Dive: The Hybrid Preprocessing Path
The core challenge was a "Hardware vs. Accuracy" trade-off. The DMP Di1's hardware ISP (Image Signal Processor) was fast but introduced letterboxing that distorted the YOLOv8s aspect ratio, dropping detection confidence to near-zero.
The Solution:
I designed a hybrid pipeline where:
- 1.BiSeNetV2 (Segmentation) remained on the hardware ISP stretch for maximum throughput.
- 2.YOLOv8s (Detection) was diverted to a custom CPU-based letterboxing path.
- 3.CMA Repacking: I implemented contiguous memory (CMA) staging to feed USB YUYV data into the ISP as if it were a local sensor, bypassing driver bottlenecks.
Evaluation & Metrics
- Performance: Stable 4.5 to 5.0 FPS dual-model concurrency.
- Latency: End-to-end (Glass-to-Dashboard) under 200ms.
- Accuracy Recovery: YOLO confidence restored from <0.10 (distorted) to >0.87 (letterboxed) for critical track obstacles.
- Reliability: Validated 60+ minute continuous run without memory leaks or frame drops.
Key Decisions & Trade-offs
- C++ over Python: Ported the entire research pipeline to native C++ to minimize overhead and access the low-level V4L2 and NPU SDKs directly.
- Docker-Based Toolchain: Built a local Docker cross-compilation environment (via Rosetta) to bypass reliance on slow, offline build machines, reducing build-deploy cycles from 15 minutes to 2 minutes.
- Manual Memory Management: Replaced unstable OpenCV `cv::resize` calls with custom C++ loops to ensure stability on the target's ARM architecture.
Development Timeline
- **Phase 1 (Orchestration):** Used AI agents to scaffold the build system (`di1.sh`) and handle redundant boilerplate for the MJPEG streaming server.
- **Phase 2 (Correction):** When AI-suggested preprocessing logic failed to account for NPU-specific memory alignment, I took over the memory-mapping and ISP configuration manually.
- **Phase 3 (Optimization):** Shipped a level-based logging system to mitigate a "Disk Full" crash caused by high-frequency profiling logs during long-run testing.